WM8762
Production Data
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
8
8
ns
ns
ns
20
40:60
1.5
60:40
12
Time from MCLK stopping to power
down.
µs
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
LRCIN
DIN
tBCY
tLRSU
tDS
tLRH
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
40
ns
BCKIN pulse width high
BCKIN pulse width low
16ns
16ns
LRCIN set-up time to BCKIN rising
edge
tLRSU
8
8
ns
ns
LRCIN hold time from BCKIN rising
edge
tLRH
DIN set-up time to BCKIN rising edge
DIN hold time from BCKIN rising edge
tDS
tDH
8
8
ns
ns
PD Rev 4.2 July 2006
7
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
