WM8753L
Advanced Information
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC,
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
TMCLKY
54
ns
TMCLKDS
60:40
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC,
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
10
10
27
ns
ns
ns
MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING
tdbpu
DBVDD
AVDD/DCVDD
Power-on-Reset
(internal)
MODE/GPIO3
CSB/GPIO5
tpusetup
tpuhold
AI Rev 3.1 June 2004
13
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
