Production Data
WM8750L
REVISION HISTORY
DATE
RELEASE
DESCRIPTION OF CHANGES
AIF Master mode timing update (tDDA).
PAGES
14
18/11/11
4.4
Noted BCLK edge should coincide with MCLK falling edge for best ADC
performance.
14, 40
Register name corrections for consistency with Register Map / WISCE™ - LIZC,
RIZC, DEEMPH, MOUTVOL
21, 22, 31, 35
26
Noted maximum recommended gain settings for ALC operation in differential
input mode.
Noted ADCDAT output is undefined logic state after power-up
Noted BCLK invert is not supported for ADC operation.
40
44
44
Noted DCVDD must be ≤ 1.5V for Right-Justified 16-bit or Right-Justified 20-bit
digital audio interface modes.
Replaced undefined term “DSP late” with “DSP Mode-B”.
Noted 1-sample delay in 88.2k, 88.235k and 96k ADC modes.
46
47
4
Order codes updated from WM8750LSEFL and WM8750LSEFL/R to
WM8750CLSEFL and WM8750CLSEFL/R to reflect change to copper wire
bonding.
14/05/12
14/05/12
4.4
4.4
Package diagram changed to DM101.A
63
PD, Rev 4.4, August 2012
65
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
