Production Data
WM8750L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC,
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
21
21
ns
ns
ns
54
60:40
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC,
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
10
10
27
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
PD, Rev 4.4, August 2012
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
