Production Data
WM8741
Figure 8 DVDD Power up Sequence
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, TA_max = +125oC, TA_min = -25oC, DVDDmax = 3.6V, DVDDmin = 3.0V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD level to POR rising
edge (DVDD rising)
Vpor_hi
Vpor_lo
Measured from DGND
Measured from DGND
1.86
1.83
V
V
DVDD level to POR falling
edge (DVDD falling)
Table 7 Digital POR Timing
In a real application the designer is unlikely to have control of the relative power up sequence of
AVDD and DVDD. The POR circuit ensures a reasonable delay between applying power to the
device and Device Ready.
Figure 7 and Figure 8 show typical power up scenarios in a real system. DVDD must be established
before the device can be written to. Any writes to the device before device ready will be ignored.
Note: DVDD must be established before the MCLK is started. This will ensure all synchronisation
circuitry within the device is fully initialised and ready.
AVDD must be established before the device will output any signal. Whilst the device will output
signal as soon as the Internal Analogue PORB indicates device ready, normal operation is not
possible until the VMID pin has reached the midrail voltage.
PD, Rev 4.2, October 2009
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
