Production Data
WM8741
REGISTER
ADDRESS
R0
BITS
NAME
DEFAULT
DESCRIPTION
[4:0]
5
LAT[4:0]
UPDATE
00 (0dB)
0
LSBs of attenuation data for left channel in 0.125dB steps. See Table
25 for details.
DACLLSB
Attenuation
00h
Attenuation data load control for left channel.
0 = Store LAT[4:0] value but don’t update
1 = Store LAT[4:0] and update attenuation on registers 0-3
Table 53 R0 DACL LSB Attenuation Control Register
REGISTER
ADDRESS
R1
BITS
NAME
DEFAULT
DESCRIPTION
[4:0]
5
LAT[9:5]
UPDATE
00 (0dB)
0
MSBs of attenuation data for left channel in 4dB steps. See Table 25
for details.
DACLMSB
Attenuation
01h
Attenuation data load control for left channel.
0 = Store LAT[9:5] value but don’t update
1 = Store LAT[9:5] and update attenuation on registers 0-3
Table 54 R1 DACL MSB Attenuation Control Register
REGISTER
ADDRESS
R2
BITS
NAME
DEFAULT
DESCRIPTION
[4:0]
5
RAT[4:0]
UPDATE
00 (0dB)
0
LSBs of attenuation data for right channel in 0.125dB steps. See
Table 25 for details.
DACRLSB
Attenuation
Attenuation data load control for right channel.
0 = Store RAT[4:0] value but don’t update
02h
1 = Store RAT[4:0] and update attenuation on registers 0-3
Table 55 R2 DACR LSB Attenuation Control Register
REGISTER
ADDRESS
R3
BITS
NAME
DEFAULT
DESCRIPTION
[4:0]
5
RAT[9:5]
UPDATE
00 (0dB)
0
MSBs of attenuation data for right channel in 4dB step. See Table 25
for details.
DACRMSB
Attenuation
Attenuation data load control for right channel.
0 = Store RAT[9:5] value but don’t update
03h
1 = Store RAT[9:5] and update attenuation on registers 0-3
Table 56 R3 DACR MSB Attenuation Control Register
PD, Rev 4.2, October 2009
45
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
