WM8738
Production Data
DIGITAL AUDIO INTERFACE TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKH
TMCLKL
TMCLKY
10
10
27
ns
ns
ns
tBCH
tBCL
BCLK
tBCY
LRCLK
tLRSU
tLRH
tDD
SDATO
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
80
40
40
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
BCLK rising edge
tLRH
tDD
10
10
ns
ns
SDATO propagation delay
from BCLK falling edge
PD Rev 4.3 November 2004
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
