WM8734
Production Data
PIN DESCRIPTION - QFN
PIN
1
NAME
MCLK
NC
TYPE
Digital Input
Do Not Connect
Supply
DESCRIPTION
Master Clock Input (MCLK)
Test Pin, must be left unconnected
Digital Core VDD
2
3
DCVDD
DGND
DBVDD
NC
4
Ground
Digital GND
5
Supply
Digital Buffers VDD
6
Do Not Connect
Test Pin, must be left unconnected
7
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
NC
Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1)
Digital Input
DAC Digital Audio Data Input
Digital Input/Output DAC Sample Rate Left/Right Clock. Pull Down (see Note 1)
Digital Output
ADC Digital Audio Data Output
Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Analogue Output
Analogue Output
Supply
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Left Channel Line Output
NC
NC
NC
LOUT
ROUT
AVDD
AGND
VMID
NC
Right Channel Line Output
Analogue VDD
Ground
Analogue GND
Analogue Output
Do Not Connect
Do Not Connect
Analogue Input
Analogue Input
Digital Input
Mid-rail reference decoupling point
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
NC
RLINEIN
LLINEIN
MODE
CSB
Digital Input
3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low,
Pull up (see Note 1)
27
28
SDIN
SCLK
Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input
Digital Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Note: It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
PD Rev 4.1 November 2006
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