WM8731 / WM8731L
PIN DESCRIPTION
Production Data
28 PIN
SSOP
1
28 PIN
QFN
5
NAME
TYPE
DESCRIPTION
DBVDD
CLKOUT
BCLK
Supply
Digital Output
Digital Input/Output
Digital Input
Digital Buffers VDD
2
6
Buffered Clock Output
3
7
Digital Audio Bit Clock, Pull Down, (see Note 1)
DAC Digital Audio Data Input
4
8
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
5
9
Digital Input/Output
Digital Output
Digital Input/Output
Supply
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
ADC Digital Audio Data Output
ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
Headphone VDD
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
8
9
Analogue Output
Analogue Output
Ground
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
10
11
12
13
14
15
16
17
18
19
20
21
22
Analogue Output
Analogue Output
Supply
Left Channel Line Output
ROUT
Right Channel Line Output
AVDD
Analogue VDD
AGND
Ground
Analogue GND
VMID
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Digital Input
Mid-rail reference decoupling point
Electret Microphone Bias
MICBIAS
MICIN
Microphone Input (AC coupled)
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
RLINEIN
LLINEIN
MODE
CSB
Digital Input
3-Wire MPU Chip Select/ 2-Wire MPU interface address
selection, active low, Pull up (see Note 1)
23
24
25
26
27
28
27
28
1
SDIN
SCLK
Digital Input/Output
Digital Input
Digital Input
Digital Output
Supply
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
XTI/MCLK
XTO
2
3
DCVDD
DGND
Digital Core VDD
4
Ground
Digital GND
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
PD, Rev 4.8, April 2009
w
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
