WM8731 / WM8731L
Production Data
ELECTRICAL CHARACTERISTICS – WM8731
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
Output HIGH
VOH
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
Vth
VIH
VOL
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
Line Input to ADC
VVMID
RVMID
AVDD/2
50k
V
Ω
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
90
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
A-weighted, 0dB gain
@ fs = 48kHz
85
85
A-weighted, 0dB gain
@ fs = 96kHz
90
88
A-weighted, 0dB gain
@ fs = 48kHz,
AVDD = 2.7V
Dynamic Range (Note 3)
Total Harmonic Distortion
DR
A-weighted, -60dB full
scale input
90
dB
THD
-1dB input, 0dB gain
-84
0.006
50
-74
dB
%
0.02
Power Supply Rejection Ratio
PSRR
1kHz, 100mVpp
dB
20Hz to 20kHz,
100mVpp
45
ADC channel separation
Programmable Gain
1kHz input
1kHz input
90
0
dB
dB
-34.5
+12
Rsource < 50Ω
Guaranteed Monotonic
0dB, 1kHz input
0dB gain
Programmable Gain Step Size
Mute attenuation
1.5
80
dB
dB
Ω
Input Resistance
RINLINE
CINLINE
20k
10k
30k
15k
10
12dB gain
Input Capacitance
pF
PD, Rev 4.8, April 2009
7
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
