WM8731 / WM8731L
Production Data
MASTER AND SLAVE MODE OPERATION
The WM8731/L can be configured as either a master or slave mode device. As a master mode
device the WM8731/L controls sequencing of the data and clocks on the digital audio interface. As a
slave device the WM8731/L responds with data to the clocks it receives over the digital audio
interface. The mode is set with the MS bit of the control register as shown in Table 16.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Digital Audio Interface
Format
Table 16 Programming Master/Slave Modes
As a master mode device the WM8731/L controls the sequencing of data transfer (ADCDAT,
DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses
the timing generated from either its on-board crystal or the MCLK input as the reference for the clock
and data transitions. This is illustrated in Figure 31. ADCDAT is always an output from and DACDAT
is always an input to the WM8731/L independent of master or slave mode.
BCLK
ADCLRC
DSP
WM8731
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Note: ADC and DAC can run at different rates
Figure 31 Master Mode
As a slave device the WM8731/L sequences the data transfer (ADCDAT, DACDAT) over the digital
audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is
illustrated in Figure 32.
BCLK
ADCLRC
DSP
WM8731
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Note: The ADC and DAC can run at different rates
Figure 32 Slave Mode
Note that the WM8731/L relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section
for detailed information.
PD, Rev 4.8, April 2009
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