WM8731 / WM8731L
Production Data
MASTER CLOCK TIMING
tXTIL
XTI/MCLK
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
XTI/MCLK System clock pulse width
high
tXTIH
tXTIL
tXTIY
18
18
ns
ns
ns
XTI/MCLK System clock pulse width
low
XTI/MCLK System clock cycle time
XTI/MCLK Duty cycle
54
40:60
60:40
XTI/MCLK
CLKOUT
tCOP
CLKOUT
(DIV X2)
Figure 2 Clock Out Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
CLKOUT propagation delay from
XTI/MCLK falling edge
tCOP
0
10
ns
PD, Rev 4.9, October 2012
15
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
