WM8731 / WM8731L
PIN DESCRIPTION
Production Data
28 PIN
SSOP
1
28 PIN
QFN
5
NAME
TYPE
DESCRIPTION
Digital Buffers VDD
DBVDD
CLKOUT
BCLK
Supply
Digital Output
Digital Input/Output
Digital Input
Buffered Clock Output
2
6
Digital Audio Bit Clock, Pull Down, (see Note 1)
DAC Digital Audio Data Input
3
7
4
8
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
ADC Digital Audio Data Output
ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
Headphone VDD
5
9
Digital Input/Output
Digital Output
Digital Input/Output
Supply
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
8
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
9
Analogue Output
Analogue Output
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
Left Channel Line Output
Analogue Output
Analogue Output
Supply
Right Channel Line Output
ROUT
Analogue VDD
AVDD
Analogue GND
AGND
Ground
Mid-rail reference decoupling point
Electret Microphone Bias
VMID
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Digital Input
MICBIAS
MICIN
Microphone Input (AC coupled)
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
RLINEIN
LLINEIN
MODE
3-Wire MPU Chip Select/ 2-Wire MPU interface address
selection, active low, Pull up (see Note 1)
CSB
Digital Input
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
23
24
25
26
27
28
27
28
1
SDIN
SCLK
Digital Input/Output
Digital Input
Digital Input
Digital Output
Supply
XTI/MCLK
XTO
2
Digital Core VDD
3
DCVDD
DGND
Digital GND
4
Ground
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
PD, Rev 4.9, October 2012
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