WM8729
Production Data
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 3 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 4 I2S Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8729 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8729 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8729 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCIN)
32kHz
4.096
5.6448
6.114
6.144
8.467
9.216
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
44.1kHz
48kHz
96kHz
192kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
PD Rev 4.1 June 2006
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
