WM8726
Production Data
1 BCKIN
1 BCKIN
1/fs
max 4 BCKIN's
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
1
2
15
16
15
16
MSB
LSB
Input Word Length (16 bits)
Figure 5 DSP Mode A Timing
1/fs
Max 4 BCKIN's
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
1
2
1
DIN
15
15
16
16
MSB
LSB
Input Word Length (16 bits)
Figure 6 DSP Mode B Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8726 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8726 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8726 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCIN)
32kHz
44.1kHz
48kHz
4.096
5.6448
6.144
12.288
24.576
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
9.216
18.432
36.864
96kHz
Unavailable Unavailable
192kHz
Unavailable Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
PD Rev 4.1 September 2005
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
