Production Data
WM8716
tSCKIL
SCKI
tSCKIH
Figure 2 System Clock Timing Requirements
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
SCKI System clock pulse width high
SCKI System clock pulse width low
tSCKIH
tSCKIL
13
13
ns
ns
tMLL
tMHH
ML/I2S (PIN 28)
MC/DM1 (PIN 27)
MD/DM0 (PIN 26)
CSBIWO (PIN 23)
tMCY
tMCH tMCL
tMLH
tMLS
tMDS
tMDH
LSB
tCSML
tMLCS
Figure 3 Program Register Input Timing
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MC/DM1 Pulse cycle time
MC/DM1 Pulse width LOW
MC/DM1 Pulse width HIGH
MD/DM0 Hold time
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
100
40
40
40
40
ns
ns
ns
ns
ns
ns
MD/DM0 Set-up time
ML/I2S Low level time
(See Note 3)
40 +
1SYSCLK
ML/I2S High level time
(See Note 3)
tMHH
40 +
1SYSCLK
ns
ML/I2S Hold time
tMLH
tMLS
tCSML
tMLCS
40
40
10
10
ns
ns
ns
ns
ML/I2S Set-up time
CSBIWO Low to ML/I2S low time
ML/I2S High to CSBIWO high time
Note:
3.
System clock cycle.
WOLFSON MICROELECTRONICS LTD
PD Rev 3.1 April 2001
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
