Production Data
WM8716
DIFFERENTIAL MONO MODE
Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed
stereo, mono left or mono right, as shown in Table 19.
DIFF[1:0]
B[4:5])
00
DIFFERENTIAL OUTPUT MODE
Stereo
01
Stereo reverse.
10
Mono left – differential outputs.
VOUTL is left channel.
VOUTR is the negative of left channel.
Mono right – differential outputs.
VOUTL is the negative right channel.
VOUTR is right channel.
11
Table 19 Differential Output Modes
Using these controls a pair of WM8716 devices may be used to build a ‘dual differential’ stereo
implementation with higher performance and differential output.
CLOCK LOSS DETECTOR DISABLE
CDD (REG4, B6)
L
Clock loss detector on
Clock loss detector off
R
Table 20 Clock Loss Detector Disable
When the system clock is inactive for approximately 100µs, the clock loss detector circuit detects the
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.
Setting the CDD bit disables this behaviour.
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PD Rev 4.1September 2006
17
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
