WM8714
Production Data
RIGHT JUSTIFIED MODE
The WM8714 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is
time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also
used as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected
word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of
word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
1
2
3
14 15
14 15
16
16
MSB
LSB
MSB
LSB
Figure 4 Right Justified Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8714 supports audio sampling rates from 256fs and 384fs, where fs is
the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, and 96kHz. The master
clock is used to operate the digital filters and the noise shaping circuits.
The WM8714 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8714 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK
FREQUENCY (MHZ)
(MCLK)
(LRCIN)
256fs
384fs
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
24.5761
12.288
16.9340
18.432
36.8641
96kHz
Table 1 Master Clock Frequencies Versus Sampling Rate
Notes:
1. 96kHz sample rate at either 256fs or 384fs are only supported with 5V supplies.
PD Rev 4.0 November 2004
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