WM8711BL
Production Data
PIN DESCRIPTION
PIN
1
NAME
XTI/MCLK
XTO
TYPE
Digital Input
Digital Output
Supply
DESCRIPTION
Crystal Input or Master Clock Input (MCLK)
Crystal Output
2
Digital Core VDD
3
DCVDD
DGND
Digital GND
4
Ground
Digital Buffers VDD
5
DBVDD
CLKOUT
BCLK
Supply
Buffered Clock Output
6
Digital Output
Digital Input/Output
Digital Input
Digital Input/Output
Supply
Digital Audio Bit Clock, Pull Down (see Note 1)
DAC Digital Audio Data Input
7
8
DACDAT
DACLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
Headphone VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
Analogue Output
Analogue Output
Ground
Left Channel Line Output
Analogue Output
Analogue Output
Supply
Right Channel Line Output
ROUT
Analogue VDD
AVDD
Analogue GND
AGND
Ground
Mid-rail reference decoupling point
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull up (see Note 1)
VMID
Analogue Output
Analogue Input
Analogue Input
Digital Input
Digital Input
RLINEIN
LLINEIN
MODE
3-Wire MPU Chip Select/ 2-Wire MPU interface address
selection, active low, Pull up (see Note 1)
CSB
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
23
24
SDIN
SCLK
Digital Input/Output
Digital Input
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
PD, Rev 4.2, December 2011
444
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