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WM8591
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
ADC/DACMCLK System clock
pulse width high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
ADC/DACMCLK System clock
pulse width low
ADC/DACMCLK System clock
cycle time
27
ADC/DACMCLK Duty cycle
40:60
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
DACBCLK
ADCBCLK
ADCLRC
DACLRC
DOUT
DVD
Controller
WM8591
CODEC
DIN
Figure 2 Audio Interface – Master Mode
PP Rev 1.0 May 2005
9
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
