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WM8591GEDS/RV 参数 Datasheet PDF下载

WM8591GEDS/RV图片预览
型号: WM8591GEDS/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192千赫立体声CODEC [24 BIT, 192 KHZ STEREO CODEC]
分类和应用:
文件页数/大小: 50 页 / 495 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8591  
Product Preview  
Figure 17 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)  
Figure 18 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)  
CONTROL INTERFACE OPERATION  
The WM8591 is controlled by writing to registers through a serial control interface. A control word  
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is  
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control  
register. The control interface operates as a 2-wire MPU interface.  
2-WIRE SERIAL CONTROL  
The WM8591 supports software control via a 2-wire serial bus. Many devices can be controlled by  
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address  
of each register in the WM8591).  
The controller indicates the start of data transfer with a high to low transition on DI while CL remains  
high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond  
to the start condition and shift in the next eight bits on DI (7-bit address + Read/Write bit, MSB first).  
If the device address received matches the address of the WM8591 and the R/W bit is ‘0’, indicating  
a write, then the WM8591 responds by pulling DI low on the next clock pulse (ACK). If the address is  
not recognised or the R/W bit is ‘1’, the WM8591 returns to the idle condition and wait for a new start  
condition and valid address.  
Once the WM8591 has acknowledged a correct address, the controller sends the first byte of control  
data (B15 to B8, i.e. the WM8591 register address plus the first bit of register data). The WM8591  
then acknowledges the first data byte by pulling DI low for one clock pulse. The controller then sends  
the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8591  
acknowledges again by pulling DI low.  
PP Rev 1.0 May 2005  
22  
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