WM8591
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REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
3
DACBCP
0
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity
0001010
DAC Interface Control
R11 (0Bh)
3
ADCBCP
0
0001011
ADC Interface Control
The WL[1:0] bits are used to control the input word length.
REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
Word Length
5:4
DACWL
[1:0]
10
0001010
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
DAC Interface Control
R11 (0Bh)
5:4
ADCWL
[1:0]
10
0001011
ADC Interface Control
Note: If 32-bit mode is selected in right justified mode, the WM8591 defaults to 24 bits.
In all modes, the data is signed 2’s complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8591 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is
high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC.
MASTER MODES
Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC
Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8591. In Slave
mode ADCLRC and ADCBCLK are inputs to WM8591.
REGISTER ADDRESS
R12 (0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
8
ADCMS
1
Audio Interface Master/Slave Mode
select for ADC:
0001100
0 : Slave Mode
1: Master Mode
Interface Control
Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC
Master mode DACLRC and DACBCLK are outputs and are generated by the WM8591. In Slave
mode DACLRC and DACBCLK are inputs to WM8591.
REGISTER ADDRESS
R12 (0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
7
DACMS
0
Audio Interface Master/Slave Mode
select for DAC:
0001100
0 : Slave Mode
1: Master Mode
Interface Control
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT
In ADC Master mode the WM8591 generates ADCLRC and ADCBCLK, in DAC master mode the
WM8591 generates DACLRC and DACBCLK. These clocks are derived from the master clock
(ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are
set by ADCRATE and DACRATE respectively.
PP Rev 1.0 May 2005
24
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
