Production Data
WM8580
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Recovered Channel Status bit-2.
2
CPY_N
-
0 = Copyright is asserted for this data.
1 = Copyright is not asserted for this data.
Note this signal is inverted and will cause an interrupt on logic 0.
Recovered Channel Status bit-3
0 = Recovered S/PDIF data has no pre-emphasis.
1 = Recovered S/PDIF data has pre-emphasis
Indicates recovered S/PDIF clock frequency:
00 = Invalid
3
DEEMPH
-
5:4
REC_FREQ
[1:0]
--
01 = 96kHz / 88.2kHz
10 = 48kHz / 44.1kHz
11 = 32kHz
6
0
UNLOCK
PWDN
-
Indicates that the S/PDIF Clock Recovery circuit is unlocked or
that the input S/PDIF signal is not present.
0 = Locked onto incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream or the incoming
S/PDIF stream is not present.
R50
PWRDN 1
32h
0
Chip Powerdown Control (works in tandem with the other
powerdown registers):
0 = All digital circuits running, outputs are active
1 = All digital circuits in power save mode, outputs muted
ADC powerdown:
1
ADCPD
1
0 = ADC enabled
1 = ADC disabled
4:2
DACPD[2:0]
111
DAC powerdowns (0 = DAC enabled, 1 = DAC disabled)
DACPD[0] = DAC1
DACPD[1] = DAC2
DACPD[2] = DAC3
6
0
ALLDACPD
OSCPD
1
0
Overrides DACPD[3:0]
0 = DACs under control of DACPD[3:0]
1= All DACs are disabled.
OSC power down
R51
PWRDN 2
33h
0 = OSC enabled
1 = OSC disabled
1
2
3
PLLAPD
PLLBPD
SPDIFPD
1
1
1
0 = PLLA enabled
1 = PLLA disabled
0 = PLLB enable
1 = PLLB disable
S/PDIF Clock Recovery PowerDown
0 = S/PDIF enabled
1 = S/PDIF disabled
4
5
SPDIFTXD
SPDIFRXD
1
1
S/PDIF Transmitter powerdown
0 = S/PDIF Transmitter enabled
1 = S/PDIF Transmitter disabled
S/PDIF Receiver powerdown
0 = S/PDIF Receiver enabled
1 = S/PDIF Receiver disabled
PD Rev 4.3 August 2007
89
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
