Production Data
WM8580
ADC FEATURES
ADC HIGH-PASS FILTER DISABLE
The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be
disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ADC high-pass filter disable
0 = high-pass filter enabled
1 = high-pass filter disabled
R29
ADC Control 1
1Dh
4
ADCHPD
0
Table 29 ADC Functions Register
ADC OVERSAMPLING RATE SELECT
The internal ADC signal processing operates at an oversampling rate of 128fs for all MCLK:LRCLK
ratios. The exception to this is for operation with a 128fs or 192fs master clock, where the internal
oversampling rate of the ADC is 64fs.
For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the
ADCOSR bit. This changes the ADC signal processing oversampling rate from 128fs to 64fs.
Similarly, for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set
the ADCOSR bit to change the oversampling rate from 64fs to 32fs.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ADC oversample rate select
0 = 128/64x oversampling
1 = 64/32x oversampling
R29
ADC Control 1
1Dh
3
ADCOSR
0
Table 30 ADC Functions Register
ADC MUTE
As with the DAC, each ADC channel also has a mute control bit, which mutes the inputs to the ADC.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R29
ADC Control 1
1Dh
0
AMUTEL
0
ADC Mute select
0 : Normal Operation
1: mute ADC left
1
2
AMUTER
0
0
ADC Mute select
0 : Normal Operation
1: mute ADC right
AMUTEALL
ADC Mute select
0 : Normal Operation
1: mute both ADC channels
Table 31 ADC Mute Register
PD Rev 4.3 August 2007
39
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
