WM8569
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By default, ADCLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally
change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of
ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the
polarity of ADCBCLK to the inverse of that shown in Figure 11 to Figure 17
REGISTER ADDRESS
0001100
BIT
LABEL
DEFAULT
DESCRIPTION
ADCBCLK Polarity (DSP Modes):
0: normal BCLK polarity
5
ADCBCP
0
Interface Control
1: inverted BCLK polarity
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. As an output it indicated 1024 consecutive
zero samples to the DAC. By default selecting the MUTE to represent if the DAC has received more
than 1024 midrail samples will cause the MUTE to be asserted as a softmute on the DAC. Disabling
the decode block will cause any logical high on the MUTE pin to apply a softmute to the DAC.
REGISTER ADDRESS
0001100
BIT
LABEL
DEFAULT
DESCRIPTION
MUTE Pin Decode Disable:
0: MUTE pin decode enable
1: MUTE pin decode disable
6
MPD
0
ADC Control
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation
control registers
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
7:0
LDA[7:0]
11111111
(0dB)
Digital Attenuation data for Left channel DACL in 0.5dB steps. See
Table 9
Digital
Attenuation
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA in intermediate latch (no change to output)
1: Store LDA and update attenuation on all channels
DACL
0000001
7:0
8
RDA[6:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Right channel DACR in 0.5dB steps. See
Table 9
Digital
Attenuation
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA in intermediate latch (no change to output)
1: Store RDA and update attenuation on all channels.
DACR
0001000
7:0
8
MASTDA
[7:0]
11111111
(0dB)
Digital Attenuation data for all DAC channels in 0.5dB steps. See
Table 9
Master
Digital
Attenuation
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
(all channels)
PP Rev 1.1 December 2005
28
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
