WM8569
Production Data
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 ADC and DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
28
40:60
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
Figure 2 Audio Interface – Master Mode
PD Rev 4.0 June 2006
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