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WM8522GEDS 参数 Datasheet PDF下载

WM8522GEDS图片预览
型号: WM8522GEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的6通道DAC,具有1.7Vrms线路驱动器 [24-bit, 192kHz 6-Channel DAC with 1.7Vrms Line Driver]
分类和应用: 驱动器
文件页数/大小: 39 页 / 394 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Pre-Production  
WM8522  
DAC DIGITAL VOLUME CONTROL  
The DAC volume may also be adjusted in the digital domain using independent digital attenuation  
control registers  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
0000000  
7:0  
LDA1[7:0]  
11111111  
(0dB)  
Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See  
Table 16  
Digital  
Attenuation  
DACL1  
8
UPDATE  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store LDA1 in intermediate latch (no change to output)  
1: Store LDA1 and update attenuation on all channels  
0000001  
7:0  
8
RDA1[6:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation data for Right channel DACR1 in 0.5dB steps.  
See Table 16.  
Digital  
Attenuation  
DACR1  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store RDA1 in intermediate latch (no change to output)  
1: Store RDA1 and update attenuation on all channels.  
0000100  
7:0  
8
LDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See  
Table 16  
Digital  
Attenuation  
DACL2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store LDA2 in intermediate latch (no change to output)  
1: Store LDA2 and update attenuation on all channels.  
0000101  
7:0  
8
RDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation data for Right channel DACR2 in 0.5dB steps.  
See Table 16  
Digital  
Attenuation  
DACR2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store RDA2 in intermediate latch (no change to output)  
1: Store RDA2 and update attenuation on all channels.  
0000110  
7:0  
8
LDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See  
Table 16  
Digital  
Attenuation  
DACL3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store LDA3 in intermediate latch (no change to output)  
1: Store LDA3 and update attenuation on all channels.  
0000111  
7:0  
8
RDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation data for Right channel DACR3 in 0.5dB steps.  
See Table 16  
Digital  
Attenuation  
DACR3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store RDA3 in intermediate latch (no change to output)  
1: Store RDA3 and update attenuation on all channels.  
0001000  
7:0  
8
MASTDA  
[7:0]  
11111111  
(0dB)  
Digital Attenuation data for all DAC channels in 0.5dB steps. See  
Table 16  
Master  
Digital  
Attenuation  
UPDATE  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0: Store gain in intermediate latch (no change to output)  
1: Store gain and update attenuation on all channels.  
(all channels)  
Note:  
When MCLK is removed, digital volume settings are re-set to default (0dB). When MCLK is re-applied, the user  
must write the desired volume level to the volume control registers.  
PP Rev 3.1 May 2006  
29  
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