WM8522
Pre-Production
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DSP/
DECODER
WM8522
DAC
LRCLK
DIN1/2/3
3
Figure 2 Audio Interface - Master Mode
BCLK
(Output)
tDL
LRCLK
(Output)
DIN1/2/3
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay
from BCLK falling edge
tDL
0
10
ns
ns
ns
DIN1/2/3 setup time to
BCLK rising edge
tDST
tDHT
10
10
DIN1/2/3 hold time from
BCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
PP Rev 3.1 May 2006
8
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
