Production Data
WM8501
RIGHT JUSTIFIED MODE
The WM8501 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is
time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also
used as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCLKs per LRCLK period is 2 times the selected
word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of
word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
Figure 4 Right Justified Mode Timing Diagram
DSP MODE
A DSP compatible, time division multiplexed format is also supported by the WM8501. This
format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of
predetermined word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCLK, and
DSP mode is auto-detected by the shorter than normal duration of the LRCLK. If LRCLK is of 4
BCLK or less duration, the DSP compatible format is selected. Mode A and Mode B clock formats
are supported, selected by the state of the FORMAT pin.
1 BCLK
1 BCLK
1/fs
max 4 BCLK's
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
1
2
15
16
15
16
MSB
LSB
Input Word Length (16 bits)
Figure 5 DSP Mode A Timing
PD, Rev 4.2, July 2009
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
