Production Data
WM8326
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
GP5_EINT
GPIO5 interrupt.
4
0
(Trigger is controlled by GP5_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO4 interrupt.
GP4_EINT
GP3_EINT
GP2_EINT
GP1_EINT
3
2
1
0
0
0
0
0
(Trigger is controlled by GP4_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO3 interrupt.
(Trigger is controlled by GP3_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO2 interrupt.
(Trigger is controlled by GP2_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO1 interrupt.
(Trigger is controlled by GP1_INT_MODE)
Note: Cleared when a ‘1’ is written.
Register 4015h Interrupt Status 5
REGISTER
ADDRESS
BIT
LABEL
IRQ_OD
DEFAULT
DESCRIPTION
REFER TO
R16407
(4017h) IRQ
Config
IRQ pin configuration
0 = CMOS
1
1
1 = Open Drain (integrated pull-up)
IRQ pin output mask
0 = Normal
IM_IRQ
0
0
1 = IRQ output is masked
Register 4017h IRQ Config
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R16408
(4018h)
System
Interrupts
Mask
IM_PS_INT
Interrupt mask.
15
1
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
IM_TEMP_INT
IM_GP_INT
14
13
12
11
1
1
1
1
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
IM_ON_PIN_IN
T
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
IM_WDOG_INT
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
PD, June 2012, Rev 4.0
159
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