Production Data
WM8326
25 WATCHDOG TIMER
The WM8326 includes a Watchdog Timer designed to detect a possible software fault condition
where the host processor has locked up. The Watchdog Timer is a free-running counter driven by the
internal RC oscillator.
The Watchdog Timer is enabled by default; it can be enabled or disabled by writing to the
WDOG_ENA register bit. The Watchdog behaviour in SLEEP is configurable; it can either be set to
continue as normal or to be disabled. The Watchdog behaviour in SLEEP is determined by the
WDOG_SLPENA bit.
The watchdog timer duration is set using WDOG_TO. The watchdog timer can be halted for debug
purposes using the WDOG_DEBUG bit.
The Watchdog reset source is selectable between Software and Hardware triggers. (Note that the de-
selected reset source has no effect.) If the Watchdog is not reset within a programmable timeout
period, this is interpreted by the WM8326 as a fault condition. The Watchdog Timer then either
triggers a Device Reset, or issues a WAKE request or raises an Interrupt. This primary action is
determined by the WDOG_PRIMACT register field.
If the Watchdog is not reset within a further timeout period of the Watchdog counter, a secondary
action is triggered. The secondary action taken at this point is determined by the WDOG_SECACT
register field.
The Watchdog reset source is selected using the WDOG_RST_SRC register bit. When Software
WDOG reset source is selected, the Watchdog is reset by writing a ‘1’ to the WDOG_RESET field.
When Hardware WDOG reset source is selected, the Watchdog is reset by toggling a GPIO pin that
has been configured as a Watchdog Reset Input (see Section 21).
If a Device Reset is triggered by the watchdog timeout, the WM8326 asserts the R¯¯E¯S¯E¯T¯ pin, resets
the internal control registers (excluding the RTC) and initiates a start-up sequence. Note that,
following a Device Reset, the action taken on subsequent timeout of the Watchdog Timer will be
determined by the WDOG_PRIMACT register. If the watchdog timeout fault persists, then a maximum
of 6 Device Reset attempts will be made. See Section 24. If the watchdog timeout occurs more than 6
times, the WM8326 will remain in the OFF state until the next valid ON state transition event occurs.
Note that the Watchdog control registers are locked by the WM8326 User Key. These registers can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Watchdog Timer Enable
R16388
(4004h)
WDOG_ENA
15
1
0 = Disabled
Watchdog
1 = Enabled (enables the watchdog; does
not reset it)
Protected by user key
Watchdog Pause
0 = Disabled
WDOG_DEBU
G
14
0
1 = Enabled (halts the Watchdog timer for
system debugging)
Protected by user key
Watchdog Reset Source
0 = Hardware only
WDOG_RST_S
RC
13
12
11
1
0
0
1 = Software only
Protected by user key
Watchdog SLEEP Enable
0 = Disabled
WDOG_SLPE
NA
1 = Controlled by WDOG_ENA
Protected by user key
Watchdog Software Reset
0 = Normal
WDOG_RESE
T
1 = Watchdog Reset (resets the watchdog,
if WDOG_RST_SRC = 1)
Protected by user key
PD, June 2012, Rev 4.0
135
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
