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WM8326GEFL/V 参数 Datasheet PDF下载

WM8326GEFL/V图片预览
型号: WM8326GEFL/V
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 255 页 / 1340 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8326  
21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO)  
21.1 GENERAL DESCRIPTION  
The WM8326 has 12 general-purpose input/output (GPIO) pins, GPIO1 - GPIO12. These can be  
configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down  
resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can  
be tri-stated and can also be used to trigger Interrupts.  
The function of each GPIO pin is selected individually. Different voltage power domains are selectable  
on a pin by pin basis for GPIOs 1-12. Input de-bounce is automatically implemented on selected  
GPIO functions.  
Note that, when GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC (see Section 18),  
then the normal GPIO functionality cannot be supported on the affected pin(s). It is recommended  
that the respective GPIO(s) are tri-stated, as described in Section 21.3.  
21.2 GPIO FUNCTIONS  
The list of GPIO functions supported by the WM8326 is contained in Table 52 (for input functions) and  
Table 53 (for output functions). The input functions are selected when the respective GPn_DIR  
register bit is 1. The output functions are selected when the respective GPn_DIR register bit is 0.  
The selected function for each GPIO pin is selected by writing to the respective GPn_FN register bits.  
All functions are available on all GPIO pins. The polarity of each input or output GPIO function can be  
selected using the applicable GPn_POL register bit.  
The available power domains for each pin are specific to different GPIOs.  
The de-bounce time for the GPIO input functions is determined by the GPn_FN field. Some of the  
input functions allow a choice of de-bounce times, as detailed in Table 52.  
The register controls for configuring the GPIO pins are defined in Section 21.3.  
GPn_FN  
GPIO INPUT  
FUNCTION  
DESCRIPTION  
DE-BOUNCE  
TIME  
GPIO  
GPIO input. Logic level is read from the  
GPn_LVL register bits. See Section 21.3.  
0h  
1h  
2h  
32s to 64s  
4ms to 8ms  
32ms 64ms  
ON/OFF  
Request  
Control input for requesting an ON/OFF state  
transition. See Section 11.3.  
Under default polarity (GPn_POL=1), a rising  
edge requests the ON state and a falling edge  
requests the OFF state.  
SLEEP/WAKE  
Request  
Control input for requesting a SLEEP/WAKE  
state transition. See Section 11.3.  
3h  
4h  
32s to 64s  
32ms to 64ms  
Under default polarity (GPn_POL=1), a rising  
edge requests the SLEEP state and a falling  
edge requests the WAKE transition to the ON  
state.  
SLEEP  
Request  
Control input for requesting a SLEEP state  
transition. See Section 11.3.  
5h  
6h  
7h  
32s to 64s  
32s to 64s  
32s to 64s  
Under default polarity (GPn_POL=1), a rising  
edge requests the SLEEP state and a falling  
edge has no effect.  
ON Request  
Control input for requesting an ON state  
transition. See Section 11.3.  
Under default polarity (GPn_POL=1), a rising  
edge requests the ON state and a falling edge  
has no effect.  
Watchdog  
Reset  
Control input for resetting the Watchdog Timer.  
See Section 25.  
PD, June 2012, Rev 4.0  
109  
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