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WM8326GEFL/RV 参数 Datasheet PDF下载

WM8326GEFL/RV图片预览
型号: WM8326GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 255 页 / 1340 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8326GEFL/RV的Datasheet PDF文件第147页浏览型号WM8326GEFL/RV的Datasheet PDF文件第148页浏览型号WM8326GEFL/RV的Datasheet PDF文件第149页浏览型号WM8326GEFL/RV的Datasheet PDF文件第150页浏览型号WM8326GEFL/RV的Datasheet PDF文件第152页浏览型号WM8326GEFL/RV的Datasheet PDF文件第153页浏览型号WM8326GEFL/RV的Datasheet PDF文件第154页浏览型号WM8326GEFL/RV的Datasheet PDF文件第155页  
Production Data  
WM8326  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
OTP_READ  
Selects READ command for the selected memory  
page(s).  
8
0
0 = No action  
1 = Read Command  
Protected by security key.  
OTP_READ_L  
VL [1:0]  
Selects the Margin Level for READ or VERIFY OTP  
commands.  
7:6  
00  
00 = Normal  
01 = Reserved  
10 = Margin 1  
11 = Margin 2  
Protected by security key.  
OTP_BULK  
Selects the number of memory pages for ICE / OTP  
commands.  
5
0
0 = Single Page  
1 = All Pages  
OTP_PAGE  
[1:0]  
Selects the single memory page for ICE / OTP  
commands (when OTP_BULK=0).  
1:0  
00  
If OTP is selected (OTP_MEM = 1):  
00 = Page 0  
01 = Page 1  
10 = Page 2  
11 = Page 3  
If ICE is selected (OTP_MEM = 0):  
00 = Page 2  
01 = Page 3  
10 = Page 4  
11 = Reserved  
Register 400Ah OTP Control  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R16396  
GP12_LVL  
GPIO12 level.  
11  
0
(400Ch)  
GPIO Level  
When GP12_FN = 0h and GP12_DIR = 0, write to this  
bit to set a GPIO output.  
Read from this bit to read GPIO input level.  
When GP12_POL is 0, the register contains the  
opposite logic level to the external pin.  
GP11_LVL  
GP10_LVL  
GPIO11 level.  
10  
0
0
When GP11_FN = 0h and GP11_DIR = 0, write to this  
bit to set a GPIO output.  
Read from this bit to read GPIO input level.  
When GP11_POL is 0, the register contains the  
opposite logic level to the external pin.  
GPIO10 level.  
9
When GP10_FN = 0h and GP10_DIR = 0, write to this  
bit to set a GPIO output.  
Read from this bit to read GPIO input level.  
When GP10_POL is 0, the register contains the  
opposite logic level to the external pin.  
PD, June 2012, Rev 4.0  
151  
w
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