Production Data
WM8326
ADDRESS
BIT
LABEL
DESCRIPTION
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
IM_UV_INT
0
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 64 Primary Interrupt Status and Mask Bits
23.2 SECONDARY INTERRUPTS
The following sections define the secondary interrupt status and control bits associated with each of
the primary interrupt bits defined in Table 64.
23.2.1 POWER STATE INTERRUPT
The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The
secondary interrupt bits are defined in Table 65.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16402
(4012h)
BIT
LABEL
PS_POR_EINT
DESCRIPTION
Power On Reset interrupt
(Rising Edge triggered)
2
Interrupt Status
2
Note: Cleared when a ‘1’ is written.
PS_SLEEP_OFF_EINT
PS_ON_WAKE_EINT
IM_PS_POR_EINT
SLEEP or OFF interrupt (Power state
transition to SLEEP or OFF states)
1
0
2
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
ON or WAKE interrupt (Power state
transition to ON state)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
R16410
(401Ah)
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
2 Mask
Default value is 1 (masked)
Interrupt mask.
IM_PS_SLEEP_OFF_EINT
IM_PS_ON_WAKE_EINT
1
0
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 65 Power State Interrupts
23.2.2 THERMAL INTERRUPTS
The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26.
The secondary interrupt bit is defined in Table 66.
PD, June 2012, Rev 4.0
123
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
