Production Data
WM8326
ADDRESS
R16396
(400Ch)
BIT
11
10
9
LABEL
GP12_LVL
GP11_LVL
GP10_LVL
GP9_LVL
GP8_LVL
GP7_LVL
GP6_LVL
GP5_LVL
GP4_LVL
GP3_LVL
GP2_LVL
GP1_LVL
DEFAULT
DESCRIPTION
GPIOn level.
0
0
0
0
0
0
0
0
0
0
0
0
When GPn_FN = 0h and GPn_DIR
= 0, write to this bit to set a GPIO
output.
GPIO Level
8
Read from this bit to read GPIO
input level.
7
6
When GPn_POL is 0, the register
contains the opposite logic level to
the external pin.
5
4
3
2
1
0
Table 55 GPIO Level Register
The power domain for each GPIO is controlled using the GPn_PWR_DOM registers as described in
Table 56.
The selected power domain for each GPIO affects the maximum input voltage that can be supported
on the respective pin(s). Note that this is also applicable when GPIO10, GPIO11 or GPIO12 are used
as inputs to the AUXADC (see Section 18). The input voltage at the GPIO pin must not exceed the
voltage of the respective power domain.
ADDRESS
R16440
(4038h)
BIT
LABEL
DEFAULT
DESCRIPTION
GPIO1 Power Domain select
0 = DBVDD
GP1_PWR_DO
M
11
0
GPIO1 Control
1 = VPMIC (LDO12)
GPIO2 Power Domain select
0 = DBVDD
R16441
(4039h)
GP2_PWR_DO
M
11
11
11
11
11
11
11
11
11
0
0
0
0
0
0
0
0
0
GPIO2 Control
1 = VPMIC (LDO12)
GPIO3 Power Domain select
0 = DBVDD
R16442
(403Ah)
GP3_PWR_DO
M
GPIO3 Control
1 = VPMIC (LDO12)
GPIO4 Power Domain select
0 = DBVDD
R16443
(403Bh)
GP4_PWR_DO
M
GPIO4 Control
1 = PVDD
R16444
(403Ch)
GP5_PWR_DO
M
GPIO5 Power Domain select
0 = DBVDD
GPIO5 Control
1 = PVDD
R16445
(403Dh)
GP6_PWR_DO
M
GPIO6 Power Domain select
0 = DBVDD
GPIO6 Control
1 = PVDD
R16446
(403Eh)
GP7_PWR_DO
M
GPIO7 Power Domain select
0 = DBVDD
GPIO7 Control
1 = VPMIC (LDO12)
GPIO8 Power Domain select
0 = DBVDD
R16447
(403Fh)
GP8_PWR_DO
M
GPIO8 Control
1 = VPMIC (LDO12)
GPIO9 Power Domain select
0 = DBVDD
R16448
(4040h)
GP9_PWR_DO
M
GPIO9 Control
1 = VPMIC (LDO12)
GPIO10 Power Domain select
0 = DBVDD
R16449
(4041h)
GP10_PWR_D
OM
GPIO10
1 = PVDD
PD, June 2012, Rev 4.0
113
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
