Production Data
WM8321
14.3.2 START-UP FROM ICE MEMORY (DEVELOPMENT MODE)
Development mode is selected if a logic high level (referenced to the LDO12 VPMIC voltage) is
present on SCLK2. This should be implemented using a pull-up resistor. See Section 14.3.4 for
details of the External ICE Memory connection.
If development mode is selected, then the WM8321 performs a check for valid ICE data; if the ICE is
not connected or contains invalid data, then the WM8321 remains in the OFF power state. The ICE
data is deemed valid is the ICE_VALID_DATA field contains the value A596h.
The WM8321 also performs a check for valid contents in the OTP_CUST_ID field in development
mode; if the OTP_CUST_ID field is set to zero, then the WM8321 remains in the OFF power state. A
non-zero OTP_CUST_ID field is used to confirm valid ICE contents.
Note that, if a GPIO pin is configured in ICE memory as “Power On/Off request” (GPn_FN=02h), then
inverted (active low) polarity should be selected for that GPIO (GPn_POL=0). The non-inverted
(active high) polarity cannot be fully supported for this function in development mode.
This restriction is only applicable in development mode, and applies only to the GPIO “Power On/Off
request” function. See Section 21 for details of the GPIO pin configuration registers.
The non-inverted (active high) polarity can be supported for the GPIO “Power On/Off request” function
in development mode if the corresponding GPn_POL register bit in the OTP memory is set to 1. Note
that, if the OTP memory is unprogrammed, the GPn_POL bits will default to 0.
14.3.3 START-UP FROM DCRW REGISTER SETTINGS
Under default settings, the bootstrap configuration data is always loaded when an ON transition is
scheduled. For development purposes, this can be disabled by clearing the RECONFIG_AT_ON
register bit. (Note that RECONFIG_AT_ON only selects whether Page 2/3/4 data is loaded; Page 0/1
data is always loaded from OTP whenever an ON transition is scheduled.)
When RECONFIG_AT_ON = 1, the bootstrap data is reloaded from either the ICE or OTP when an
ON transition is scheduled. The logic level on SCLK2 is checked to determine whether the ICE or the
OTP memory should be used. If RECONFIG_AT_ON = 0, then the latest contents of the DCRW are
used to configure the start-up sequence.
Note that, when WM8321 start-up is scheduled using this method, the contents of OTP_CUST_ID is
still checked for valid contents. In development mode, the ICE_VALID_DATA field is also checked.
See Section 14.3.2 for details.
Note that the RECONFIG_AT_ON control register is locked by the WM8321 User Key. This register
can only be changed by writing the appropriate code to the Security register, as described in
Section 12.4.
ADDRESS
R16390 (4006h)
Reset Control
BIT
LABEL
DEFAULT
DESCRIPTION
RECONFIG_A
T_ON
Selects if the bootstrap configuration
data should be reloaded when an ON
transition is scheduled
15
1
0 = Disabled
1 = Enabled
Protected by user key
Table 19 Bootstrap Configuration Reload Control
14.3.4 EXTERNAL ICE MEMORY CONNECTION
The recommended component for the external ICE is the Microchip 24AA32A, which provides 32
bytes of memory space. The ICE interfaces with the WM8321 via the SCLK2 and SDA2 pins, and
initiates an I2C transfer of data from the ICE when required. The necessary electrical connections for
this device are illustrated in Figure 19. The WM8321 assumes an EEPROM device ID of 1010 0001
(A1h) for ICE read cycles.
The ICE memory contents are defined similarly to Pages 2, 3 and 4 of the DCRW memory contents
listed in Section 14.6.
PD, February 2012, Rev 4.0
51
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
