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WM8321GEFL/RV 参数 Datasheet PDF下载

WM8321GEFL/RV图片预览
型号: WM8321GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 253 页 / 1578 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8321  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R16422  
(4026h)  
RTC Trim  
RTC_TRIM  
[9:0]  
RTC frequency trim. Value is a 10bit fixed point <4,6>  
2's complement number. MSB Scaling = -8Hz.  
9:0  
00_0000_0  
000  
The register indicates the error (in Hz) with respect to  
the ideal 32768Hz) of the input crystal frequency.  
Protected by security key.  
Register 4026h RTC Trim  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R16429  
(402Dh)  
AuxADC  
Data  
AUX_DATA_S  
RC [3:0]  
AUXADC Data Source  
1 = GPIO10  
15:12  
0000  
2 = GPIO11  
3 = GPIO12  
5 = Chip Temperature  
7 = PVDD voltage  
All other values are Reserved  
AUXADC Measurement Data  
Voltage (mV) = AUX_DATA x 1.465  
ChipTemp (°C) = (498 - AUX_DATA) / 1.09  
AUX_DATA  
[11:0]  
11:0  
0000_0000  
_0000  
Register 402Dh AuxADC Data  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R16430  
(402Eh)  
AuxADC  
Control  
AUX_ENA  
AUXADC Enable  
15  
0
0 = Disabled  
1 = Enabled  
Note - this bit is reset to 0 when the OFF power state is  
entered.  
AUX_CVT_EN  
A
AUXADC Conversion Enable  
14  
0
0 = Disabled  
1 = Enabled  
In automatic mode, conversions are enabled by setting  
this bit.  
In manual mode (AUX_RATE = 0), setting this bit will  
initiate a conversion; the bit is reset automatically after  
each conversion.  
AUX_SLPENA  
AUXADC SLEEP Enable  
0 = Disabled  
12  
0
1 = Controlled by AUX_ENA  
AUX_RATE  
[5:0]  
AUXADC Conversion Rate  
0 = Manual  
5:0  
00_0000  
1 = 2 samples/s  
2 = 4 samples/s  
3 = 6 samples/s  
31 = 62 samples/s  
32 = Reserved  
33 = 16 samples/s  
34 = 32 samples/s  
35 = 48 samples/s  
63 = 496 samples/s  
Register 402Eh AuxADC Control  
PD, February 2012, Rev 4.0  
165  
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