WM8253
Production Data
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. The output buffer from the RLCDAC also
requires decoupling at pin VRLC/VBIAS when this is configured as an output.
POWER SUPPLY
The WM8253 runs from a 3.3V single supply.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit low.
All the internal registers maintain their previously programmed value in power down mode and the
Control Interface inputs remain active.
OPERATING MODES
Table 3 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
TIMING
REQUIREMENTS
REGISTER
CONTENTS WITH
CDS
REGISTER
CONTENTS
WITHOUT CDS
Monochrome/
Colour Line-by-Line
MCLK max = 36MHz SetReg1: 03(hex)
SetReg1: 01(hex)
1
Yes
Yes
6MSPS
MCLK:VSMP ratio is
6:1
Fast Monochrome/
Colour Line-by-Line
MCLK max = 18MHz Identical to Mode
Identical to
Mode 1
2
6MSPS
1 plus SetReg3:
bits 5:4 must be
set to 0(hex)
MCLK:VSMP ratio is
3:1
Maximum speed
Monochrome/
Colour Line-by-Line
MCLK max = 12MHz CDS not possible
SetReg1: 41(hex)
3
4
No
6MSPS
MCLK:VSMP ratio is
2:1
Slow Monochrome/
Colour Line-by-Line
MCLK max = 36MHz Identical to
Identical to
Mode 1
Yes
4.5MSPS
Mode 1
MCLK:VSMP ratio is
2n:1, n 4
Table 3 WM8253 Operating Modes
PD, Rev 4.1, August 2011
18
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
