WM8253
Production Data
PIN DESCRIPTION
PIN
NO
NAME
TYPE
DESCRIPTION
Analogue ground pin (0V)
1
2
3
4
AGND2
DVDD1
VSMP
MCLK
Supply
Supply
Digital Core supply (3.3V)
Video sample synchronisation pulse.
Digital input
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
5
6
7
8
9
DGND
SEN
Supply
Enables the serial interface when high.
Digital I/O supply (2.5V-3.3V), all digital I/O pins.
Serial data input.
Digital input
Supply
DVDD2
SDI
Digital input
Digital input
Serial clock.
SCK
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below.
A
B
C
D
10
11
12
13
OP[0]
OP[1]
Digital output
Digital output
Digital output
Digital output
d12
d13
d14
d15
d8
d4
d5
d6
d7
d0
d9
d1
d2
d3
OP[2]
d10
d11
OP[3]/SDO
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
Analogue supply (3.3V)
Analogue ground (0V).
14
15
16
AVDD
AGND1
VRB
Supply
Supply
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
17
VRT
Analogue output
This pin must be connected to AGND via a decoupling capacitor.
18
19
NC
Not Connected
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
VRLC/VBIAS
Video input pin.
20
VINP
Analogue input
PD, Rev 4.1, August 2011
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
