WM8253
Production Data
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 6.
MCLK
VSMP
VS
RS/CL (CDSREF = 00)
RS/CL (CDSREF = 01)
RS/CL (CDSREF = 10)
RS/CL (CDSREF = 11)
Figure 6 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above.
The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for
each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B).
In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC
can be multiplexed by control of the INTM[1:0] bits as shown in Table 1.
INTM[1:0]
DESCRIPTION
Red offset and gain registers are applied to offset DAC and PGA
(DACR[7:0] and PGAR[7:0])
00
Green offset and gain registers applied to offset DAC and PGA
(DACG[7:0] and PGAG[7:0])
01
10
11
Blue offset and gain registers applied to offset DAC and PGA
(DACB[7:0] and PGAB[7:0])
Reserved.
Table 1 Offset DAC and PGA Register Control
The gain characteristic of the WM8253 PGA is shown in Figure 7. Figure 8 shows the maximum input
voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.0V).
PD, Rev 4.1, August 2011
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
