WM8199
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 32MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion rate
16
0
MSPS
Vp-p
Vp-p
V
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.4
4.08
Input signal limits (see Note 2)
Full-scale transition error
VIN
AVDD
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
20
mV
Zero-scale transition error
Gain = 0dB;
mV
PGA[7:0] = 4B(hex)
Differential non-linearity
Integral non-linearity
DNL
INL
1.25
36
1
LSB
LSB
Channel to channel gain matching
Total output noise
%
Min Gain
Max Gain
5
LSB rms
LSB rms
25
References
Upper reference voltage
VRT
VRB
VRX
VRTB
2.85
1.35
1.65
1.5
V
V
V
V
Ω
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
1.4
1.6
1.6
50
2
Ω
mA
Ω
2
VRLC Hi-Z leakage current
RLCDAC resolution
VRLC = 0 to AVDD
AVDD=5V
1
µA
4
bits
V/step
V/step
V
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
VRLCSTEP
VRLCSTEP
VRLCBOT
0.25
0.17
0.39
RLCDAC output voltage at
AVDD=5V
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
VRLCTOP
VRLCTOP
0.26
4.14
2.81
25
V
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
AVDD=5V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
V
VRLC deviation
mV
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
INL
0.1
0.5
1
0.25
2.02
-260
+260
LSB
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
PD Rev 4.3 March 2007
6
w