WM8198
Production Data
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output.
V2
=
V1 + {260mV (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain. The PGA transfer characteristic varies with the value
of the PGAMODE register bit.
If PGAMODE = 0 (wide gain range PGA mode - default):
V3
If PGAMODE = 1 (high resolution PGA mode):
V3 V2 (1 + PGA[8:0]x4/511).............................................. Eqn. 5b
=
V2 416/(566 - PGA[8:0]) ………................................... Eqn. 5a
=
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS
D1[15:0] = INT{ (V3 /VFS
D1[15:0] = INT{ (V3 /VFS
)
)
)
65535} + 32767......... PGAFS[1:0] = 00 or 01 Eqn. 6
65535} ............................... PGAFS[1:0] = 11 Eqn. 7
65535} + 65535.................. PGAFS[1:0] = 10 Eqn. 8
where the ADC full-scale range, VFS = 3V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[15:0] = D1[15:0] ..............................................................(INVOP = 0) Eqn. 9
D2[15:0] = 65535 – D1[15:0].................................................(INVOP = 1) Eqn. 10
OUTPUT FORMATS
The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by
setting control bit MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable
by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing
Diagrams section.
Figure 12 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 13 shows the output data
formats for Mode 3. Table 1 summarises the output data obtained for each format.
MCLK
MCLK
8+8-BIT
OUTPUT
8+8-BIT
OUTPUT
A
B
A
B
4+4+4+4-BIT
OUTPUT
4+4+4+4-BIT
OUTPUT
A
B
C
D
A B A B C
D
Figure 12 Output Data Formats
Figure 13 Output Data Formats
(Mode 3)
(Modes 1 − 2, 4 − 6)
PD Rev 4.0 June 2004
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
