WM8196
Production Data
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 5. The diagrams
are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown
as R, G and B respectively. X denotes invalid data.
16.5 MCLK PERIODS
MCLK
VSMP
INPUT VIDEO
OP[7:0]
(DEL = 00)
RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB
BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB
GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB
RA RB GA GB BA BB RA RB GA GB BA BB RA RB GB GA BA BB RA RB GA GB BA BB RA RB GA GB BA BB
OP[7:0]
(DEL = 01)
OP[7:0]
(DEL = 10)
OP[7:0]
(DEL = 11)
Figure 21 Mode 1 Operation
Figure 22 Mode 2 Operation
PD Rev 4.3 March 2007
23
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
