WM5615
Pin Description
PIN
NAME
DIN
SCLK
CS
FUNCTION
1
2
3
4
Serial data input.
Serial clock input.
Chip select, active low.
Serial data output for daisy-
chaining.
DOUT
5
6
7
8
AGND
REFIN
VOUT
VDD
Analogue ground.
Reference input.
DAC output.
Positive power supply.
Timing Diagram
CS
th(CSHO)
SCLK
tw(CS)
th(CSH1)
tsu(CS1)
tw(CL)
tsu(CSS) tw(CH)
th(DH)
See note A
See note C
tsu(DS)
DIN
tpd(DOUT)
See note B
DOUT
Previous LSB
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimise clock feedthrough.
B. Data input from preceeding conversion cycle.
C. Sixteenth SCLK falling edge.
Detailed Description
General Function
DIN
SCLK
DOUT
CS
The WM5615 uses a resistor string network buffered
with a single-supply CMOS op amp in a fixed gain of x2 to
convert 10-bit digital data to analogue voltage levels (see
Block Diagram). The topology of the WM5615 makes the
output the same polarity as the reference input (see Ta-
ble 1).
REFIN
+
-
+
-
VOUT
R
An internal reset circuit forces the DAC register to reset
to all 0s on power-up.
R
VDD
AGND
0.1µF
+5V
Figure 1 - Typical Operating Circuit
Wolfson Microelectronics
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
