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WM2636CD 参数 Datasheet PDF下载

WM2636CD图片预览
型号: WM2636CD
PDF下载: 下载PDF文件 查看货源
内容描述: 12位串行输入电压输出DAC ,内置基准 [12-bit Serial Input Voltage Output DAC with Internal Reference]
分类和应用:
文件页数/大小: 10 页 / 395 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM2636  
Production Data  
DEVICE DESCRIPTION  
GENERAL FUNCTION  
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data  
to analogue voltage levels (see Block Diagram). The output voltage is determined by the  
reference input voltage and the input code according to the following relationship:  
CODE  
Output voltage = 2  
1111  
(
VREF  
)
4096  
INPUT  
OUTPUT  
1111  
1111  
4095  
4096  
2
(
(
VREF  
)
)
:
:
1000  
1000  
0111  
0000  
0001  
0000  
1111  
2049  
4096  
2
VREF  
0000  
1111  
2048  
4096  
2
(
VREF  
)
= VREF  
2047  
2
2
(
(
VREF  
)
)
4096  
:
:
0000  
0000  
0000  
0001  
0000  
1
VREF  
4096  
0000  
0V  
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2  
POWER ON RESET  
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.  
BUFFER AMPLIFIER  
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive  
a 2kload with a 100pF load capacitance.  
SERIAL INTERFACE  
Explanation of data transfer:  
First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts  
shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of  
SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved  
to the DAC latch which updates the voltage output to the new level.  
The serial interface of the device can be used in two basic modes:  
four wire (with chip select)  
three wire (without chip select)  
Using chip select (four wire mode), it is possible to have more than one device connected to  
the serial port of the data source (DSP or microcontroller). If there is no need to have more  
than one device on the serial bus, then NCS can be tied low.  
SERIAL CLOCK AND UPDATE RATE  
Figure 1 shows the device timing. The maximum serial rate is:  
1
fSCLKmax =  
= 20MHz  
tWCH min+ tWCL min  
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC  
settling time to 12 bits limits the update rate for large input step transitions.  
WOLFSON MICROELECTRONICS LTD  
PD Rev 1.0 July 1999  
7