WM2630
Production Data
SERIAL INTERFACE
tWL tWH
3
SCLK
X
tSUD
X
1
2
4
16
X
tHD
DIN
D15
D15 *
D14
D14 *
D13
D1
D0
D0 *
X
X
2
DOUT
X
D13 *
D12 *
D1 *
tWHFS tSUFSCLK
tSUC16-FS
* DIN data from previous word
(delayed by 16 clock cycles)
FS
(
µ
C MODE)
tWLFS
FS
No high to low transitions
(DSP MODE)
Figure 1 Timing Diagram
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Setup time, FS pin low before first falling edge of SCLK
tSUFSCLK
tC16-FS
8
ns
ns
Setup time, 16th falling clock edge after FS low to rising edge of FS (only
used in microcontroller mode)
10
Pulse duration, LOADB low
tWLOADB
tWH
10
16
16
8
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SCLK high
Pulse duration, SCLK low
tWL
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
tSUD
tHD
5
tWHFS
tWLFS
ts
10
10
Pulse duration, FS low
DAC Output settling time
see Dynamic DAC Specifications
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
