W9412G6JH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A11.
28 32,
A0 A11
35 41
Address
Column address: A0 A8. (A10 is used for Auto-precharge)
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
26, 27
BA0, BA1
Bank Select
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
Data Input/ Output
DQ0 DQ15
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
LDQS,
UDQS
16,51
24
Data Strobe
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
CS
RAS
CAS
, ,
Command inputs (along with CS ) define the command
being entered.
23, 22, 21
20, 47
Command Inputs
Write Mask
WE
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
LDM, UDM
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK,
CLK
Differential Clock
Inputs
45, 46
44
CLK
.
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
CKE
Clock Enable
49
VREF
VDD
VSS
Reference Voltage VREF is reference voltage for inputs.
1, 18, 33
34, 48, 66
Power
Power for logic circuit inside DDR SDRAM.
Ground for logic circuit inside DDR SDRAM.
Ground
Power for I/O
Buffer
Separated power from VDD, used for output buffer, to
improve noise.
3, 9, 15, 55, 61
6, 12, 52, 58, 64
VDDQ
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffer, to
improve noise.
14, 17, 19, 25,
42, 43, 50, 53
NC
No Connection
No connection
Publication Release Date: Nov. 29, 2011
- 7 -
Revision A03
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