W90N745CD/W90N745CDG
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES................................................................................................................................. 2
PIN DIAGRAM ............................................................................................................................ 7
PIN ASSIGNMENT ..................................................................................................................... 8
PIN DESCRIPTION................................................................................................................... 13
FUNCTIONAL DESCRIPTION ................................................................................................. 24
6.1
6.2
ARM7TDMI CPU CORE............................................................................................... 24
System Manager........................................................................................................... 25
6.2.1 Overview ........................................................................................................................25
6.2.2 System Memory Map......................................................................................................25
6.2.3 Address Bus Generation ................................................................................................28
6.2.4 Data Bus Connection with External Memory ..................................................................28
6.2.5 Bus Arbitration................................................................................................................37
6.2.6 Power Management .......................................................................................................38
6.2.7 Power-On Setting ...........................................................................................................41
6.2.8 System Manager Control Registers Map........................................................................41
6.3
6.4
External Bus Interface .................................................................................................. 56
6.3.1 EBI Overview..................................................................................................................56
6.3.2 SDRAM Controller..........................................................................................................56
6.3.3 EBI Control Registers Map.............................................................................................60
Cache Controller........................................................................................................... 79
6.4.1 On-Chip RAM.................................................................................................................79
6.4.2 Non-Cacheable Area......................................................................................................79
6.4.3 Instruction Cache............................................................................................................80
6.4.4 Data Cache ....................................................................................................................82
6.4.5 Write Buffer ....................................................................................................................84
6.4.6 Cache Control Registers Map.........................................................................................84
6.5
6.6
6.7
6.8
Ethernet MAC Controller............................................................................................... 92
6.5.1 EMC Functional Description...........................................................................................93
6.5.2 EMC Register Mapping ................................................................................................103
GDMA Controller ........................................................................................................ 158
6.6.1 GDMA Functional Description ......................................................................................158
6.6.2 GDMA Register Map ....................................................................................................159
USB Host Controller ................................................................................................... 168
6.7.1 USB Host Functional Description .................................................................................168
6.7.2 USB Host Controller Registers Map .............................................................................169
USB Device Controller................................................................................................ 192
6.8.1 USB Endpoints.............................................................................................................192
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