W90N745CD/W90N745CDG
6.9
Audio Controller
The audio controller consists of I²S/AC-link protocol to interface with external audio CODEC.
One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right
channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO
and memory.
The following are the property of the DMA.
•
•
•
Always 8-beat incrementing burst
Always bus lock when 8-beat incrementing burst
When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
An AHB master port and an AHB slave port are offered in audio controller.
6.9.1 I²S Interface
The I²S interface signals are shown as Figure 6.9.1
MCLK
BCLK
Audio
Audio
Codec
LRCLK
DOUT
DIN
Controller
Figure 6.9.1 The interface signal of I²S
Publication Release Date: September 22, 2006
Revision A2
- 231 -
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