W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Control Frame Receive Interrupt high indicates EMC
receives a flow control frame. The CFR only available while EMC
is operating on full duplex mode.
If the CFR is high and EnCFR of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the CFR status.
[14]
CFR
1’b0: The EMC doesn’t receive the flow control frame.
1’b1: The EMC receives a flow control frame.
[13:12]
Reserved
The Receive Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through RxDMA during packet reception process. Reset
EMC is recommended while RxBErr status is high.
If the RxBErr is high and EnRxBErr of MIEN register is enabled,
the RxINTR will be high. Write 1 to this bit clears the RxBErr
status.
[11]
RxBErr
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
The Receive Descriptor Unavailable Interrupt high indicates that
there is no available Rx descriptor for packet reception and
RxDMA will stay at Halt state. Once, the RxDMA enters the Halt
state, S/W must issues a write command to RSDR register to
make RxDMA leave Halt state while new Rx descriptor is
available.
[10]
RDU
If the RDU is high and EnRDU of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the RDU status.
1’b0: Rx descriptor is available.
1’b1: Rx descriptor is unavailable.
The DMA Early Notification Interrupt high indicates the EMC has
received the Length/Type field of the incoming packet.
If the DENI is high and EnDENI of MIEN register is enabled, the
RxINTR will be high. Write 1 to this bit clears the DENI status.
[9]
DENI
1’b0: The Length/Type field of incoming packet has not received
yet.
1’b1: The Length/Type field of incoming packet has received.
Publication Release Date: September 22, 2006
- 139 -
Revision A2
WINBOND [ WINBOND ]
